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The electronics industry is nearing the limit of how many transistors can fit on a single computer chip. As a solution, manufacturers are exploring building chips vertically rather than just expanding them horizontally.
Instead of cramming smaller transistors onto one surface, the industry is considering stacking multiple layers of transistors and semiconducting materials, like converting a single-story house into a skyscraper. These multilayered chips could handle much more data and perform more complex tasks than current electronics.
A major challenge, however, is the platform used to build these chips. Currently, thick silicon wafers are the main base for growing high-quality, single-crystal semiconducting elements. Any stackable chip design would have to include thick silicon layers for each level, which slows down communication between the layers.
Now, engineers at MIT have developed a new multilayered chip design that eliminates the need for silicon wafer substrates and operates at temperatures low enough to protect the underlying circuitry.
Published today in the journal Nature, the MIT team detailed a method to create a multilayered chip with alternating layers of high-quality semiconducting material grown directly on top of each other.
This method allows engineers to build high-performance transistors and memory and logic components on any crystalline surface, not just bulky silicon wafers. Without thick silicon substrates, multiple semiconducting layers can communicate faster and more efficiently, the researchers explain.
The team envisions using this method to develop AI hardware, such as stacked chips for laptops or wearables, that could match the speed and power of today’s supercomputers and store data comparable to physical data centers.
“This breakthrough unlocks immense potential for the semiconductor industry, enabling chip stacking without traditional limitations,” says study author Jeehwan Kim, an associate professor of mechanical engineering at MIT. “This could lead to massive improvements in computing power for AI, logic, and memory applications.”
The study’s MIT co-authors include first author Ki Seok Kim, Seunghwan Seo, Doyoon Lee, Jung-El Ryu, Jekyung Kim, Jun Min Suh, June-chul Shin, Min-Kyu Song, Jin Feng, and Sangho Lee, along with collaborators from Samsung Advanced Institute of Technology, Sungkyunkwan University in South Korea, and the University of Texas at Dallas.
Seed Pockets
In 2023, Kim’s group developed a technique to grow high-quality semiconducting materials on amorphous surfaces, similar to the varied topography of semiconducting circuitry on finished chips. The material they grew was a type of 2D material known as transition-metal dichalcogenides, or TMDs, which are seen as promising successors to silicon for creating smaller, high-performance transistors. These 2D materials can retain their semiconducting properties even at the atomic scale, whereas silicon’s performance drastically declines.
In their earlier work, the team grew TMDs on silicon wafers with amorphous coatings and over existing TMDs. To encourage atoms to form high-quality single-crystalline structures instead of random, polycrystalline patterns, Kim and his colleagues covered a silicon wafer with a thin film, or “mask,” of silicon dioxide patterned with tiny openings, or pockets. They then exposed the mask to a gas of atoms, finding that atoms settled into the pockets as “seeds.” These pockets restricted the seeds to grow in regular, single-crystalline patterns.
At the time, however, this method only worked at about 900 degrees Celsius.
“You have to grow this single-crystalline material below 400 degrees Celsius, otherwise the underlying circuitry is completely damaged,” Kim says. “So, we had to develop a technique to do this at temperatures lower than 400 degrees Celsius. Achieving this would have a significant impact.”
Building Up
In their new research, Kim and his team refined their technique to grow single-crystalline 2D materials at temperatures low enough to preserve the underlying circuitry. They found an unexpectedly simple solution in metallurgy—the science and art of metal production. When metallurgists pour molten metal into a mold, the liquid slowly “nucleates,” forming grains that grow and merge into a regularly patterned crystal that solidifies. Metallurgists have discovered that this nucleation occurs most easily at the edges of a mold where liquid metal is poured.
“It’s known that nucleating at the edges requires less energy and heat,” Kim explains. “We borrowed this concept from metallurgy for future AI hardware.”
The team aimed to grow single-crystalline TMDs on a silicon wafer already fabricated with transistor circuitry. They first covered the circuitry with a silicon dioxide mask, as in their previous work, then deposited TMD “seeds” at the edges of each pocket in the mask. They found that these edge seeds grew into single-crystalline material at temperatures as low as 380 degrees Celsius, whereas seeds that started growing in the center, away from the pocket edges, needed higher temperatures to form single-crystalline material.
Taking this a step further, the researchers used the new method to create a multilayered chip with alternating layers of two different TMDs—molybdenum disulfide, a promising candidate for n-type transistors, and tungsten diselenide, which has potential for p-type transistors. Both p- and n-type transistors are essential for performing logic operations. The team successfully grew both materials in single-crystalline form, directly on top of each other, without needing any intermediate silicon wafers. Kim states the method will effectively double the density of a chip’s semiconducting components, especially metal-oxide semiconductors (CMOS), the basic building blocks of modern logic circuitry.
“Our technique results in not just a 3D logic chip but also 3D memory and their combinations,” Kim says. “With our growth-based monolithic 3D method, you could grow dozens to hundreds of logic and memory layers right on top of each other, with excellent communication between them.”
“Traditional 3D chips have been made with silicon wafers in between, by drilling holes through the wafer—a process limiting the number of stacked layers, vertical alignment resolution, and yields,” adds first author Kiseok Kim. “Our growth-based method solves all these problems simultaneously.”
To further commercialize their stackable chip design, Kim has launched a company named FS2 (Future Semiconductor 2D materials).
“So far, we’ve shown this concept at a small-scale device array,” he says. “The next step is scaling up to demonstrate professional AI chip operation.”
This research is partially supported by Samsung Advanced Institute of Technology and the U.S. Air Force Office of Scientific Research.
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